cv

Contact Information

Name Robert Bao
Professional Title MS Student
Email rsbao2@illinois.edu
Phone 240-750-7079
Location Urbana, Illinois
Website https://rsbao.github.io

Experience

  • 2024 - 2026

    Research Assistant
    ECE @ UIUC
    Waferscale Silicon Photonics
    • Waferscale Silicon Photonics Systems: A Cost-Benefit Analysis and Optimization - ICCAD ‘25
    • Some other stuff under Submission
  • 2024 - Present

    Teaching Assistant
    ECE @ UIUC
    • ECE 411 - Computer Organization & Design
    • ECE 313 - Probability with Engineering Applications
    • ECE 385 - Digital Systems Lab
  • 2024 - 2024

    Pre-silicon Performance Verification Intern
    IBM
    scripting
    • Computer Architecture
    • C/C++
    • Assembly
    • Python
  • 2022 - 2024

    Course Assistant
    ECE @ UIUC
    • ECE 110 - Intro to Electronics
    • ECE 210 - Analog Signal Processing
    • ECE 220 - Computer Systems and Programming
    • ECE 385 - Digital Systems Lab
  • 2023 - 2023

    Processor Logic Design Intern
    IBM
    branch prediction modeling
    • Computer Architecture
    • C++
    • Python
  • 2023 - 2023

    Research Assistant
    HCESC @ UIUC
    Augmented reality clinical breast examination trainer using Arduino, force sensing array, and Unity

Education

  • 2024 - 2026

    Urbana, IL

    Master of Science
    University of Illinois Urbana-Champaign
    Computer Architecture
    • Computer Architecture
    • Emerging Memory/Storage Systems
  • 2021 - 2024

    Urbana, IL

    Bachelor's of Science
    University of Illinois Urbana-Champaign
    Computer Engineering
    • VLSI Design
    • Computer Architecture

Awards

  • 2024
    Promise of Excellence Fellowship
    UIUC

    Given to incoming students who demonstrate the potential to achieve great things in the field of Electrical and Computer Engineering.

Skills

Computer Engineering (Graduate Student): Computer Architecture, VLSI Design, SystemVerilog, C/C++ Programming, Operating Systems, Analog/Digital Signal Processing
Hobbies (Master): Mountain Biking

Projects

  • Superscalar, Out-of-Order RISC-V CPU

    Built a 2-way superscalar Out-Of-Order RISC-V CPU using explicit register renaming supporting RISC-V(IM) ISA. Features include Dadda multiplier, Synopsis IP divider, BTB & BHT/GShare tournament branch predictor, 4-way set-associative PLRU pipelined caches with next-line prefetcher. Verified design using random coverage, Synopsys VCS and Verdi, Spike.

    • SystemVerilog
    • Computer Architecture
  • 32-bit RISC-V Datapath Layout

    Hand laid out a bit-sliced RISC-V Datapath, starting from basic cells (NAND,NOR,DFF,etc.), progressing to ALU, register file, shifter, etc., and finally to the full datapath.

    • SystemVerilog
    • Computer Architecture