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Sr. Chip Design Intern

IBM

Pre-silicon performance verification

• Computer Architecture
• C/C++
• Assembly
• Python

Chip Design Intern

IBM

Branch prediction modeling

• Computer Architecture
• C++
• Python

Research Assistant

HCESC @ UIUC

Augmented reality clinical breast examination trainer using Arduino, force sensing array, and Unity

Course Assistant

ECE @ UIUC

• ECE 110 - Intro to Electronics
• ECE 210 - Analog Signal Processing
• ECE 220 - Computer Systems and Programming
• ECE 385 - Digital Systems Lab

MS/PhD

University of Illinois Urbana-Champaign

Computer Architecture

• Advanced VLSI Design
• Computer Architecture

Promise of Excellence Fellowship

UIUC

Given to incoming students who demonstrate the potential to achieve great things in the field of Electrical and Computer Engineering.

Superscalar, Out-of-Order RISC-V CPU

Built a 2-way superscalar Out-Of-Order RISC-V CPU using explicit register renaming supporting RISC-V(IM) ISA. Features include Dadda multiplier, Synopsis IP divider, BTB & BHT/GShare tournament branch predictor, 4-way set-associative PLRU pipelined caches with next-line prefetcher. Verified design using random coverage, Synopsys VCS and Verdi, Spike.

• SystemVerilog
• Computer Architecture

32-bit RISC-V Datapath Layout

Hand laid out a bit-sliced RISC-V Datapath, starting from basic cells (NAND,NOR,DFF,etc.), progressing to ALU, register file, shifter, etc., and finally to the full datapath.

• SystemVerilog
• Computer Architecture